AS4C256M16D3LB-12BCN - 4Gb DRAM

Product Overview

Alliance Semiconductor

Datasheet Details

Part number	AS4C256M16D3LB-12BCN
Manufacturer	Alliance Semiconductor
File Size	2.37 MB
Description	4Gb DRAM
Datasheet	AS4C256M16D3LB-12BCN Datasheet
Note	This datasheet PDF includes multiple part numbers: AS4C256M16D3LB-12BCN, AS4C256M16D3LB-12BIN. Please refer to the document for exact specifications by model.
Additional preview pages of the AS4C256M16D3LB-12BCN datasheet.

Product details

Description

Pin CK, CK CKE CS ODT RAS, CAS, WE DM (DMU), (DML) Type Input Input Input Input Input Input Function Clock : CK and CK are differential clock inputs.All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK.Output (read) data is referenced to the crossings of CK and CK Clock Enable : CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers.Taking CKE Low provides Precharge Powe

Features

- Double-data-rate architecture; two data transfers per clock cycle - The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture - Bi-directional differential data strobe (DQS and DQS) is transmitted/received with data for capturing data at the receiver - DQS is edge-aligned with data for READs; center-aligned with data for WRITEs - Differential clock inputs (CK and CK) - DLL aligns DQ and DQS transitions with CK transitions - Commands entered on each positive CK edge.

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Other Datasheets by Alliance Semiconductor

AS4C256M16D3LB-12BAN - 4Gb DRAM
AS4C256M16D3LB-12BIN - 4Gb DRAM
AS4C256M16D3L - 256M x 16 bit DDR3L Synchronous DRAM
AS4C256M16D3LA-12BIN - 256M x 16 bit DDR3L Synchronous DRAM
AS4C256M16D3A-12BIN - 256M x 16 bit DDR3 Synchronous DRAM
AS4C256M16D3B-12BCN - Double-data-rate architecture

Published: Mar 19, 2019 |