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AS4C256M16D3LB-12BAN Datasheet 4gb Dram

Manufacturer: Alliance Semiconductor

Overview: AS4C256M16D3LB-12BAN Revision History 4Gb AS4C256M16D3LB - 12BAN 96 ball FBGA PACKAGE Revision Details Rev 1.0 Preliminary datasheet Date Mar. 2018 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1/46 - Rev.1.0 Mar 2018 AS4C256M16D3LB-12BAN Specifications - Density : 4G bits - Organization : 32M words x 16 bits x 8 banks - Package : - 96-ball FBGA - Lead-free (RoHS pliant) and Halogen-free - Power supply : VDD, VDDQ = 1.35V (1.283V to 1.45V) - Backward patible to VDD, VDDQ = 1.5V ± 0.075V - Data rate : - 1600Mbps - 2KB page size - Row address: A0 to A14 - Column address: A0 to A9 - Eight internal banks for concurrent operation - Burst lengths (BL) : 8 and 4 with Burst Chop (BC) - Burst type (BT) : - Sequential (8, 4 with BC) - Interleave (8, 4 with BC) - CAS Latency (CL) : 5, 6, 7, 8, 9, 10, 11 - CAS Write Latency (CWL) : 5, 6, 7, 8 - Precharge : auto precharge option for each burst access - Driver strength : RZQ/7, RZQ/6 (RZQ = 240 Ω) - Refresh : auto-refresh, self-refresh - Refresh cycles : - Average refresh period 7.8 μs at -40°C ≤ Tc ≤ +85°C 3.

Key Features

  • - Double-data-rate architecture; two data transfers per clock cycle - The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture - Bi-directional differential data strobe (DQS and DQS) is transmitted/received with data for capturing data at the receiver - DQS is edge-aligned with data for READs; center-aligned with data for WRITEs - Differential clock inputs (CK and CK) - DLL aligns DQ and DQS transitions with CK transitions - Commands entered on each positive CK edge.

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