AS4C256M16D3LB-12BCN

AS4C256M16D3LB-12BCN Key Features

• Double-data-rate architecture; two data transfers per clock cycle
• The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and DQS) is transmitted/received with data for capturing data at the receiv
• DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
• Differential clock inputs (CK and CK)
• DLL aligns DQ and DQS transitions with CK transitions
• mands entered on each positive CK edge; data and
• Data mask (DM) for write data
• Posted CAS by programmable additive latency for better
• On-Die Termination (ODT) for better signal quality