Description
The
256K x 36 / 512K x 18. The SRAMs contain write, data, address and control registers.Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle.The burst mode feature offers the highest level of performance to the system designer, as the AS8C803600/801800 can provide four cycles of data for a single address presented to the SRAM.An internal burst address counter accepts the first cycle address from the processor,.
Features
- 256K x 36, 512K x 18 memory configurations Supports high system speed:.
- 150MHz 3.8ns clock access time.
- LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 3.3V I/O supply (VDDQ) Packaged in a JEDEC Standard 100-pin thin plastic quad flatpack (TQFP).
