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AS7C251MPFS36A - (AS7C251MPFS32A / AS7C251MPFS36A) 2.5V 1M x 32/36 pipelined burst synchronous SRAM

Download the AS7C251MPFS36A datasheet PDF. This datasheet also covers the AS7C251MPFS32A variant, as both devices belong to the same (as7c251mpfs32a / as7c251mpfs36a) 2.5v 1m x 32/36 pipelined burst synchronous sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The AS7C251MPFS32A/36A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM) device organized as 1,048,576 words x 32/36.

It incorporates a two-stage register-register pipeline for highest frequency on any given technology.

Key Features

  • Organization: 1,048,576 words × 32 or 36 bits.
  • Fast clock speeds to 200 MHz.
  • Fast clock to data access: 3.1/3.5/3.8 ns.
  • Fast OE access time: 3.1/3.5/3.8 ns.
  • Fully synchronous register-to-register operation.
  • Single-cycle deselect.
  • Asynchronous output enable control.
  • Available in 100-pin TQFP package www. DataSheet4U. com.
  • Individual byte write and global write Multiple.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (AS7C251MPFS32A_AllianceSemiconductorCorporation.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number AS7C251MPFS36A
Manufacturer Alliance Semiconductor Corporation
File Size 568.48 KB
Description (AS7C251MPFS32A / AS7C251MPFS36A) 2.5V 1M x 32/36 pipelined burst synchronous SRAM
Datasheet download datasheet AS7C251MPFS36A Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
February 2005 ® AS7C251MPFS32A AS7C251MPFS36A 2.5V 1M × 32/36 pipelined burst synchronous SRAM Features • Organization: 1,048,576 words × 32 or 36 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.1/3.5/3.8 ns • Fast OE access time: 3.1/3.5/3.8 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control • Available in 100-pin TQFP package www.DataSheet4U.com • • • • • • Individual byte write and global write Multiple chip enables for easy expansion 2.