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AS7C33512FT36A - (AS7C33512FT32A / AS7C33512FT36A) 3.3V 512K x 32/36 Flow-through synchronous SRAM

Download the AS7C33512FT36A datasheet PDF (AS7C33512FT32A included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for (as7c33512ft32a / as7c33512ft36a) 3.3v 512k x 32/36 flow-through synchronous sram.

Description

The AS7C33512FT32A/36A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as 524,288 words x 32/36.

Fast cycle times of 8.5/10/12 ns with clock access times (tCD) of 7.5/8.5/10 ns.

Three chip enable (CE) inputs permit easy memory expansion.

Features

  • Organization: 524,288 words × 32 or 36 bits Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation Asynchronous output enable control Available in 100-pin TQFP packages Individual byte write and global write Multiple chip enables for easy expansion.
  • 3.3V core power supply 2.5V or 3.3V I/O operation with separat.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (AS7C33512FT32A_AllianceSemiconductorCorporation.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number AS7C33512FT36A
Manufacturer Alliance Semiconductor Corporation
File Size 569.51 KB
Description (AS7C33512FT32A / AS7C33512FT36A) 3.3V 512K x 32/36 Flow-through synchronous SRAM
Datasheet download datasheet AS7C33512FT36A Datasheet

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Full PDF Text Transcription

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December 2004 ® AS7C33512FT32A AS7C33512FT36A 3.3V 512K × 32/36 Flow-through synchronous SRAM Features • • • • • • • • Organization: 524,288 words × 32 or 36 bits Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation Asynchronous output enable control Available in 100-pin TQFP packages Individual byte write and global write Multiple chip enables for easy expansion • • • • • 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs www.DataSheet4U.
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