The AS7C3364PFS32B and AS7C3364PFS36B are high-performance CMOS 2-Mbit synchronous Static Random Access Memory (SRAM) devices organized as 65,536 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given technology.
Features
Organization: 65,536 words × 32 or 36 bits.
Fast clock speeds to 200 MHz.
Fast clock to data access: 3.0/3.5/4.0 ns.
Fast OE access time: 3.0/3.5/4.0 ns.
Fully synchronous register-to-register operation.
Single-cycle deselect.
Asynchronous output enable control.
Available in 100-pin TQFP package www. DataSheet4U. com.
AS7C3364FT32B- (AS7C3364FT32B / AS7C3364FT36B) 3.3V 64K x 32/36 Flow Through Synchronous SRAM
AS7C3364NTD32B- (AS7C3364NTD32B / AS7C3364NTD36B) 3.3V 64K x 32/36 Pipelined SRAM
AS7C3364NTD36B- (AS7C3364NTD32B / AS7C3364NTD36B) 3.3V 64K x 32/36 Pipelined SRAM
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December 2004
®
AS7C3364PFS32B AS7C3364PFS36B
3.3V 64K X 32/36 pipeline burst synchronous SRAM
Features
• Organization: 65,536 words × 32 or 36 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control • Available in 100-pin TQFP package www.DataSheet4U.com
• • • • • • •
Linear or interleaved burst control Individual byte write and global write Snooze mode for reduced power-standby Common data inputs and data outputs Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.
AS7C3364PFS32B Datasheet
