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AS7C3364PFS36B - (AS7C3364PFS32B / AS7C3364PFS36B) 3.3V 64K X 32/36 pipeline burst synchronous SRAM

Download the AS7C3364PFS36B datasheet PDF (AS7C3364PFS32B included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for (as7c3364pfs32b / as7c3364pfs36b) 3.3v 64k x 32/36 pipeline burst synchronous sram.

Description

The AS7C3364PFS32B and AS7C3364PFS36B are high-performance CMOS 2-Mbit synchronous Static Random Access Memory (SRAM) devices organized as 65,536 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given technology.

Features

  • Organization: 65,536 words × 32 or 36 bits.
  • Fast clock speeds to 200 MHz.
  • Fast clock to data access: 3.0/3.5/4.0 ns.
  • Fast OE access time: 3.0/3.5/4.0 ns.
  • Fully synchronous register-to-register operation.
  • Single-cycle deselect.
  • Asynchronous output enable control.
  • Available in 100-pin TQFP package www. DataSheet4U. com.
  • Linear or interleaved burst control In.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (AS7C3364PFS32B_AllianceSemiconductorCorporation.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number AS7C3364PFS36B
Manufacturer Alliance Semiconductor Corporation
File Size 594.64 KB
Description (AS7C3364PFS32B / AS7C3364PFS36B) 3.3V 64K X 32/36 pipeline burst synchronous SRAM
Datasheet download datasheet AS7C3364PFS36B Datasheet
Other Datasheets by Alliance Semiconductor Corporation

Full PDF Text Transcription

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December 2004 ® AS7C3364PFS32B AS7C3364PFS36B 3.3V 64K X 32/36 pipeline burst synchronous SRAM Features • Organization: 65,536 words × 32 or 36 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control • Available in 100-pin TQFP package www.DataSheet4U.com • • • • • • • Linear or interleaved burst control Individual byte write and global write Snooze mode for reduced power-standby Common data inputs and data outputs Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.
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