EP1810 Datasheet Epld

Manufacturer: Altera

Overview: May 1999, ver. 5.

Datasheet Details

The Altera ClassicTM device family offers a solution to high-speed, lowpower logic integration.

Fabricated on advanced CMOS technology, Classic devices also have a Turbo-only version, which is described in this data sheet.

Classic devices support 100% TTL emulation and can easily integrate multiple PAL- and GAL-type devices

Classic ® EPLD Family Data Sheet s Complete device family with logic densities of 300 to 900 usable gates (see Table 1) s Device erasure and reprogramming with non-volatile EPROM configuration elements s Fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz s 24 to 68 pins available in dual in-line package (DIP), plastic J-lead chip carrier (PLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages s Programmable security bit for protec.

Part Number	Description
EP1810EPLD	COMPLEX-EPLD 48-CELL 20NS PROP DELAY
EP1800	48-Macrocell EPLD
EP1C12	FPGA
EP1C20	FPGA
EP1C3	FPGA
EP1C4	FPGA
EP1C6	FPGA
EP1K10	Programmable Logic Device
EP1K100	Programmable Logic Device
EP1K30	Programmable Logic Device