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EPM9400 - Max 9000(a) Programmable Logic Device Family (6k Gates)

Download the EPM9400 datasheet PDF. This datasheet also covers the EPM9320 variant, as both devices belong to the same max 9000(a) programmable logic device family (6k gates) family and are provided as variant models within a single manufacturer datasheet.

Description

The MAX 9000 family of in-system-programmable, high-density, highperformance EPLDs is based on Altera’s third-generation MAX architecture.

Features

  • High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX®) architecture 5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 High-density erasable programmable logic device (EPLD) family ranging from 6,000 to.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (EPM9320_AlteraCorporation.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number EPM9400
Manufacturer Altera Corporation
File Size 540.99 KB
Description Max 9000(a) Programmable Logic Device Family (6k Gates)
Datasheet download datasheet EPM9400 Datasheet

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Other Datasheets by Altera Corporation

Part Number Description
EPM9480 Max 9000(a) Programmable Logic Device Family (6k Gates)
EPM9320 Max 9000(a) Programmable Logic Device Family (6k Gates)
EPM9320A Max 9000(a) Programmable Logic Device Family (6k Gates)
EPM9560 Max 9000(a) Programmable Logic Device Family (6k Gates)
EPM9560A Max 9000(a) Programmable Logic Device Family (6k Gates)

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com ® Includes MAX 9000A MAX 9000 Programmable Logic Device Family Data Sheet December 2002, ver. 6.4 Features... ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX®) architecture 5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.
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