AD14060 Datasheet | Analog Devices

FEATURES ADSP-21060 core processor ( × 4) 480 MFLOPS peak, 320 MFLOPS sustained 25 ns instruction rate, single-cycle instruction execution- each of four processors 16 Mbit shared SRAM (internal to SHARCs) 4 gigawords addressable off-module memory Twelve 40 Mbyte/s link ports (3 per SHARC) Four 40 Mbit/s independent serial ports (one from each SHARC) One 40 Mbit/s mon serial port 5 V and 3.3 V operation 32-bit single precision and 40-bit extended precision IEEE floating point data formats, or 32-bit fixed point data format IEEE JTAG Standard 1149.1 test access port and on-chip emulation PACKAGING FEATURES 308-lead ceramic quad flatpack (CQFP) 2.05" (52 mm) body size Cavity up or down, configurable Low profile, 0.160" height Hermetic 25 Mil (0.65 mm) lead pitch 29 grams (typical) θJC = 0.36°C/W GENERAL DESCRIPTION The AD14060/AD14060L Quad-SHARC is the first in a family of high performance DSP multiprocessor modules. The core of the multiprocessor is the ADSP-21060 DSP microputer. The AD14060/AD14060L has the highest performance-to-density and lowest cost-to-performance ratios of any in its class. It is ideal for applications requiring higher levels of performance and/or functionality per unit area. The AD14060/AD14060L takes advantage of the built-in multiprocessing features of the ADSP-21060 to achieve 480 peak MFLOPS with a single chip type in a single package. The on-chip SRAM of the DSPs provides 16 Mbits of onmodule shared SRAM. The plete shared bus (48 data, Quad-SHARC® DSP Multiprocessor Family AD14060/AD14060L FUNCTIONAL BLOCK DIAGRAM CS TIMEXP LINK 1 LINK 3 LINK 4 IRQ2- 0 FLAG2, 0 CS TIMEXP LINK 1 LINK 3 LINK 4 IRQ2- 0 FLAG2, 0 CPA SPORT 1 TDI SHARC_A (ID2- 0 = 1) LINK 0 LINK 2 LINK 5 LINK 0 LINK 2 LINK 5 TDI SHARC_B (ID2- 0 = 2) CPA SPORT 1 EBOOT, LBOOT, BMS EMU CLKIN RESET SPORT 0 TCK, TMS, TRST FLAG1 FLAG3 TDO EBOOT, LBOOT, BMS EMU CLKIN RESET SPORT 0 TCK, TMS, TRST FLAG1 FLAG3 SSHWA,RACCKB, USBST(SA, DHDBRR3, 1H- B0G, D, RAETDAY4,7, - B0R,6M-...