AD1892 Datasheet | Analog Devices

a Features plete EIAJ CP-340 (CP-1201), IEC-958, AES/EBU, S/PDIF patible Digital Audio Receiver and Asynchronous Sample Rate Converter Status Pins and Microprocessor Interfaces for Stand-Alone and Microcontroller-Oriented Operation Integrated Channel Status Buffer and Q-Channel Subcode Buffer (Supports EIAJ CP-2401) 20-Bit Sample Port® Architecture Provides Superb Jitter Rejection on Input Port Sample Rate Conversion from 8 k Hz to 48 k Hz with 1:5 Upsampling Range 1:0.85 Downsampling Range 120 d B Dynamic Range - 113 d B THD+N @ 1 k Hz CRC Calculation on Q-Channel Subcode (Consumer Mode Only) and on Channel Status (Pro Mode Only) Four-Wire SPI™ patible Serial Control Port Mute Input Pin Power-Down Mode Single +5 V Supply Flexible Three-Wire Serial Data Port with Left-Justified, Right-Justified and I2 S-patible Modes 28-Lead SOIC Package APPLICATIONS DVD, DAT, MD, DCC and CD-R Recorders and Players puter Multimedia Products DAB Receivers, Automotive Digital Audio Networks Integrated Digital Receiver/Rate Converter AD1892 PRODUCT OVERVIEW The AD1892 bines a CP-1201, CP-340, IEC-958, AES/ EBU, S/PDIF patible Digital Audio Receiver (DAR) with an asynchronous sample rate converter, allowing the user to specify the output sample rate of the received digital audio information. The DAR block Features support for both Q-channel subcode information (to support CD, CD-R, MD and DAT digital audio formats) as well as Channel Status information. A microcontroller interface, with an SPI patible serial port, allows full access to the 80-bit Q-Channel subcode buffer and to the 32-bit Channel Status buffer, as well as to the control and status registers. Additionally, key status information from the ining subframes and the Channel Status buffer is reported on status output pins on the AD1892, so the AD1892 may be used in systems that do not include a microcontroller or microprocessor. The asynchronous sample rate converter block is based on market leading...