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AD7172-2 - Sigma-Delta ADC

General Description

Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate of 6.21 kSPS/channel (161 µs settling) Performance specifications 17.2 noise free bits at 31.25 kSPS 24 noise free bits at 5 SPS INL: ±2 ppm of FSR 85 dB rejection of 50 Hz and 60 Hz with 50 ms settling User configurable i

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Data Sheet Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers AD7172-2 FEATURES GENERAL DESCRIPTION Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate of 6.21 kSPS/channel (161 µs settling) Performance specifications 17.2 noise free bits at 31.25 kSPS 24 noise free bits at 5 SPS INL: ±2 ppm of FSR 85 dB rejection of 50 Hz and 60 Hz with 50 ms settling User configurable input channels 2 fully differential channels or 4 single-ended channels Crosspoint multiplexer On-chip 2.5 V reference (±2 ppm/°C drift) True rail-to-rail analog and reference input buffers Internal or external clock Power supply AVDD1 = 3.0 V to 5.5 V, AVDD2 = IOVDD = 2 V to 5.5 V Split supply with AVDD1 and AVSS at ±2.5 V or ±1.65 V ADC current: 1.