AD9640 Datasheet | Analog Devices

FEATURES - SNR = 71.8 d Bc (72.8 d BFS) to 70 MHz @ 125 MSPS - SFDR = 85 d Bc to 70 MHz @ 125 MSPS - Low power: 750 m W @ 125 MSPS - SNR = 71.6 d Bc (72.6 d BFS) to 70 MHz @ 150 MSPS - SFDR = 84 d Bc to 70 MHz @ 150 MSPS - Low power: 820 m W @ 150 MSPS - 1.8 V analog supply operation - 1.8 V to 3.3V CMOS output supply or 1.8 V LVDS output supply - Integer 1 to 8 input clock divider - IF sampling frequencies to 450 MHz - Internal ADC voltage reference - Integrated ADC sample-and-hold inputs - Flexible analog input range: 1 V p-p to 2 V p-p - Differential analog inputs with 650 MHz bandwidth - ADC clock duty cycle stabilizer - 95 d B channel isolation/crosstalk - Serial port control - User-configurable, built-in self-test (BIST) capability - Energy-saving power-down modes - Integrated receive features - Fast detect/threshold bits - posite signal monitor APPLICATIONS - munications - Diversity radio systems - Multimode digital receivers - GSM, EDGE, WCDMA, LTE, - CDMA2000, Wi MAX, TD-SCDMA - I/Q demodulation systems - Smart antenna systems - General-purpose software radios - Broadband data applications FUNCTIONAL BLOCK DIAGRAM Figure 1. PRODUCT HIGHLIGHTS 1. Integrated dual 14-bit, 80/105/125/150 MSPS ADC. 2. Fast overrange detect and signal monitor with serial output. 3. Signal monitor block with dedicated serial output mode. 4. Proprietary differential input that maintains excellent SNR per- formance for input frequencies up to 450 MHz. 5. Operation from a single 1.8 V supply and a separate digital output driver supply to acmodate 1.8 V to 3.3 V logic families. 6. A standard serial port interface that supports various product features and functions, such as data formatting (offset binary, twos plement, or gray coding), enabling the clock DCS, power-down, and voltage reference mode. 7. Pin patibility with the AD9627, AD9627-11, and the AD9600 for a simple migration from 14 bits to 12 bits, 11 bits, or 10 bits. Rev. C DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished...