Datasheet4U Logo Datasheet4U.com

ADSP-21061 - Commercial Grade SHARC DSP Microcomputer

General Description

3 SHARC Family Core Architecture 3 Memory and I/O Interface

Key Features

  • KEY.

📥 Download Datasheet

Full PDF Text Transcription for ADSP-21061 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for ADSP-21061. For precise diagrams, and layout, please refer to the original PDF.

a SUMMARY High performance signal processor for communications, graphics, and imaging applications Super Harvard Architecture Four independent buses for dual data fetch, ...

View more extracted text
uper Harvard Architecture Four independent buses for dual data fetch, instruction fetch, and nonintrusive I/O 32-bit IEEE floating-point computation units—multiplier, ALU, and shifter Dual-ported on-chip SRAM and integrated I/O peripherals—a complete system-on-a-chip Integrated multiprocessing features KEY FEATURES—PROCESSOR CORE 50 MIPS, 20 ns instruction rate, single-cycle instruction execution 120 MFLOPS peak, 80 MFLOPS sustained performance Commercial Grade SHARC DSP Microcomputer ADSP-21061/ADSP-21061L Dual data address generators with modulo and bit-reverse addressing Efficient program sequencing with zero-overhead l

More Datasheets from Analog Devices

Part Number Description
ADSP-21061L Commercial Grade SHARC DSP Microcomputer
ADSP-21060 SHARC Processor
ADSP-21060C SHARC Processor
ADSP-21060L SHARC Processor
ADSP-21060LC SHARC Processor
ADSP-21062 SHARC Processor
ADSP-21062L SHARC Processor
ADSP-21065L DSP Microcomputer
ADSP-2100A DSP Microcomputers
ADSP-2101 DSP Microcomputers