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ADSP-21061L - Commercial Grade SHARC DSP Microcomputer

Download the ADSP-21061L datasheet PDF. This datasheet also covers the ADSP-21061 variant, as both devices belong to the same commercial grade sharc dsp microcomputer family and are provided as variant models within a single manufacturer datasheet.

General Description

3 SHARC Family Core Architecture 3 Memory and I/O Interface

Key Features

  • KEY.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ADSP-21061-AnalogDevices.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
a SUMMARY High performance signal processor for communications, graphics, and imaging applications Super Harvard Architecture Four independent buses for dual data fetch, instruction fetch, and nonintrusive I/O 32-bit IEEE floating-point computation units—multiplier, ALU, and shifter Dual-ported on-chip SRAM and integrated I/O peripherals—a complete system-on-a-chip Integrated multiprocessing features KEY FEATURES—PROCESSOR CORE 50 MIPS, 20 ns instruction rate, single-cycle instruction execution 120 MFLOPS peak, 80 MFLOPS sustained performance Commercial Grade SHARC DSP Microcomputer ADSP-21061/ADSP-21061L Dual data address generators with modulo and bit-reverse addressing Efficient program sequencing with zero-overhead looping: single-cycle loop setup IEEE JTAG Standard 1149.