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SUMMARY High performance signal processor for communications,
graphics, and imaging applications Super Harvard Architecture
Four independent buses for dual data fetch, instruction fetch, and nonintrusive I/O
32-bit IEEE floating-point computation units—multiplier, ALU, and shifter
Dual-ported on-chip SRAM and integrated I/O peripherals—a complete system-on-a-chip
Integrated multiprocessing features
KEY FEATURES—PROCESSOR CORE
50 MIPS, 20 ns instruction rate, single-cycle instruction execution
120 MFLOPS peak, 80 MFLOPS sustained performance
Commercial Grade
SHARC DSP Microcomputer
ADSP-21061/ADSP-21061L
Dual data address generators with modulo and bit-reverse addressing
Efficient program sequencing with zero-overhead looping: single-cycle loop setup
IEEE JTAG Standard 1149.
ADSP-21061 Datasheet
