* KEY FEATURES
* PROCESSOR CORE 50 MIPS, 20 ns instruction rate, single-cycle instruction execution 120 MFLOPS peak, 80 MFLOPS sustained performance Commercial Grade SHARC DSP Microcomputer ADSP-21061/ADSP-21061L Dual data address generators with modulo and bit-reverse addressing Efficient prog
ADSP-21061L Datasheet (865.10 KB)
ADSP-21061L
865.10 KB
Commercial grade sharc dsp microcomputer.
a SUMMARY High performance signal processor for communications, graphics, and imaging applications Super Harvard Architecture Four independent buses f.
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