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ADSP-21267 Datasheet Preliminary Technical Data

Manufacturer: Analog Devices

Overview

www.DataSheet4U.com Preliminary Technical Data SUMMARY High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Code compatible with all other SHARC.

Key Features

  • At 150 MHz (6.65 ns) core instruction rate, the ADSP-21267 operates at 900 MFLOPS performance whether operating on fixed or floating point data 300 MMACS sustained performance at 150 MHz Code compatibility.
  • At assembly level, uses the same instruction set as other SHARC DSPs Super Harvard Architecture.
  • three independent buses for dual data fetch, instruction fetch, and nonintrusive, zerooverhead I/O 1M Bit on-chip dual-ported SRAM (0.5M Bit in block 0 and 0.5M Bit in block 1) for s.