Dual-enhanced SHARC+ high performance floating-point cores Up to 1000 MHz per SHARC+ core 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure.
SYSTEM CONTROL
SECURITY AND PROTECTION SYSTEM PROTECTION UNIT (SPU)
SYSTEM MEMORY PROTECTION UNIT (SMPU) CRYPTOGRAPHIC .
......... 3
ARM Cortex-A55 Processor ...... 5 SHARC Processor ......... 6 SHARC+ Core Architecture ...... 8 System Infrastructure ... 10 System Memory Map ... 11 Security Features ........ 14 Security Features Disclaimer .... 14 Safety Features . 15 .
Image gallery
TAGS
+
Manufacturer
Related datasheet