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ADSP-SC594 - SHARC+ Dual-Core DSP

Download the ADSP-SC594 datasheet PDF. This datasheet also covers the ADSP-21593 variant, as both devices belong to the same sharc+ dual-core dsp family and are provided as variant models within a single manufacturer datasheet.

General Description

3 ARM Cortex-A5 Processor (ADSP-SC592/SC594 Only) 5 SHARC Processor 6 SHARC+ Core Architecture 8 System Infrastructure 10 System Memory Map 11 Security

Key Features

  • Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, short word, word, and long word addressability Arm Cortex-A5 core Up to 1 GHz/1600 DMIPS with NEON/VFPv4-D16 32 kB L1 instruction and data caches with parity 256 kB L2 cache with parity Powerful DMA system with 8 MemDMAs On-chip.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ADSP-21593-AnalogDevices.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Analog Devices

Part Number Description
ADSP-SC592 SHARC+ Dual-Core DSP
ADSP-SC596 SHARC+ Dual-Core DSP
ADSP-SC598 SHARC+ Dual-Core DSP
ADSP-SC570 SHARC+ Dual-Core DSP
ADSP-SC571 SHARC+ Dual-Core DSP

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
SHARC+ Dual-Core DSP with Arm Cortex-A5 ADSP-21593/21594/ADSP-SC592/SC594 SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, short word, word, and long word addressability Arm Cortex-A5 core Up to 1 GHz/1600 DMIPS with NEON/VFPv4-D16 32 kB L1 instruction and data caches with parity 256 kB L2 cache with parity Powerful DMA system with 8 MemDMAs On-chip memory protection Integrated safety features 17 mm × 17 mm, 400-ball BGA_ED (0.