ADSP-SC592 Datasheet | Analog Devices

SHARC+ Dual-Core DSP with Arm Cortex-A5 ADSP-21593/21594/ADSP-SC592/SC594 SYSTEM Features Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, short word, word, and long word addressability Arm Cortex-A5 core Up to 1 GHz/1600 DMIPS with NEON/VFPv4-D16 32 kB L1 instruction and data caches with parity 256 kB L2 cache with parity Powerful DMA system with 8 MemDMAs On-chip memory protection Integrated safety Features 17 mm × 17 mm, 400-ball BGA_ED (0.8 mm pitch), RoHS...