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ADSP-TS201S - TigerSHARC-R Embedded Processor

Description

3 Dual Compute Blocks 4 Data Alignment Buffer (DAB) 4 Dual Integer ALU (IALU) 4 Program Sequencer 5 Interrupt Controller 5 Flexible Instruction Set 5 DSP Memory 5 External Port (Off-Chip Memory/Peripherals Interface) 6 Host Interface 6 Multiprocessor Interface 7 SDRAM Controller 7 EPROM

Features

  • Up to 600 MHz, 1.67 ns Instruction Cycle Rate 24M Bits of Internal.
  • On-Chip.
  • DRAM Memory 25×25 mm (576-Ball) Thermally Enhanced Ball Grid Array Package Dual Computation Blocks.
  • Each Containing an ALU, a Multiplier, a Shifter, a Register File, and a Communications Logic Unit (CLU) Dual Integer ALUs, providing Data Addressing and Pointer Manipulation Integrated I/O Includes 14 Channel DMA Controller, External Port, Four Link Ports, SDRAM Controller, Programmable Flag Pins, Two.

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www.DataSheet4U.com Preliminary Technical Data KEY FEATURES Up to 600 MHz, 1.67 ns Instruction Cycle Rate 24M Bits of Internal—On-Chip—DRAM Memory 25×25 mm (576-Ball) Thermally Enhanced Ball Grid Array Package Dual Computation Blocks—Each Containing an ALU, a Multiplier, a Shifter, a Register File, and a Communications Logic Unit (CLU) Dual Integer ALUs, providing Data Addressing and Pointer Manipulation Integrated I/O Includes 14 Channel DMA Controller, External Port, Four Link Ports, SDRAM Controller, Programmable Flag Pins, Two Timers, and Timer Expired Pin for System Integration 1149.
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