* 20 MIPS, 50 ns Maximum Instruction Rate Separate On-Chip Buses for Program and Data Memory Program Memory Stores Both Instructions and Data (Three-Bus Performance) Dual Data Address Generators with Modulo and Bit-Reverse Addressing Efficient Program Sequencing with Zero-Overhead Looping: Single-Cycl
ADSP2104 Datasheet (333.32 KB)
ADSP2104
333.32 KB
Low cost dsp microcomputers.
a SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual D.
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