C5002 Key Features
- Produces PCI output clocks that are individually selectable for 33.3 or 66.6 MHz under SMBus or
- Separate output buffer power supply for reduced
- input clock frequency standard 14.31818 MHz
- Output clocks frequency individually selectable via
- SSCG EMI reduction at 1.0% width
- Individual clock disables via SMBus control
- All output clocks skewed within a 500 pS window
- Cycle to Cycle jitter ± 250 pS
- Output duty cycle is automatically 50% (±10%)
- Clock feed through mode and OE pins for logic
