Datasheet4U Logo Datasheet4U.com

CY7C1381D - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

General Description

The CY7C1381D/CY7C1383D/CY7C1383F is a 3.3 V, 512K × 36 and 1M × 18 synchronous flow through SRAMs, designed to interface with high speed microprocessors with minimum glue logic.

Maximum access delay from clock rise is 6.5 ns (133 MHz version).

Key Features

  • Supports 133 MHz bus operations.
  • 512K × 36 and 1M × 18 common I/O.
  • 3.3 V core power supply (VDD).
  • 2.5 V or 3.3 V I/O supply (VDDQ).
  • Fast clock-to-output time.
  • 6.5 ns (133 MHz version).
  • Provides high performance 2-1-1-1 access rate.
  • User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences.
  • Separate processor and controller address strobes.
  • Synchronous self-timed write.
  • Asynchronous output enable.
  • CY7C.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C1381KV33 18-Mbit Flow-Through SRAM Cypress Semiconductor
CY7C1381KVE33 18-Mbit Flow-Through SRAM Cypress Semiconductor
CY7C138 4K x 8/9 Dual-Port Static RAM Cypress Semiconductor
CY7C1380BV25 512K x 36 / 1 Mb x 18 Pipelined SRAM Cypress Semiconductor
CY7C1380C 18-Mb (512K x 36/1M x 18) Pipelined SRAM Cypress Semiconductor

Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1380S 18-Mbit (512 K x 36/1 M x 18) Pipelined SRAM
CY7C1382S 18-Mbit (512 K x 36/1 M x 18) Pipelined SRAM
CY7C1383D 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383F 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1386S 18-Mbit (512 K x 36) Pipelined DCD Sync SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Not Recommended for New Designs. CY7C1381D CY7C1383D CY7C1383F 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM Features ■ Supports 133 MHz bus operations ■ 512K × 36 and 1M × 18 common I/O ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O supply (VDDQ) ■ Fast clock-to-output time ❐ 6.5 ns (133 MHz version) ■ Provides high performance 2-1-1-1 access rate ■ User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed write ■ Asynchronous output enable ■ CY7C1381D available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package. CY7C1383D available in JEDEC-standard Pb-free 100-pin TQFP.