CY2PP3210 buffer equivalent, dual 1:5 differential clock / data fanout buffer.
* Dual sets of five ECL/PECL differential outputs
* Two ECL/PECL differential inputs
* Hot-swappable/-insertable
* 50 ps output-to-output skew
* 150 p.
The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to ac.
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