CY7C1261V18 - 1.8V Synchronous Pipelined SRAM

Features

Separate independent read and write data ports.
Supports concurrent transactions.
300 MHz to 400 MHz clock for high bandwidth.
4-Word Burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 800 MHz) at 400 MHz.
Read latency of 2.5 clock cycles.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high speed.

Cypress Semiconductor

Datasheet Details

Part number	CY7C1261V18
Manufacturer	Cypress Semiconductor
File Size	404.82 KB
Description	1.8V Synchronous Pipelined SRAM
Datasheet	CY7C1261V18 Datasheet
Additional preview pages of the CY7C1261V18 datasheet.

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Full PDF Text Transcription

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CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz to 400 MHz clock for high bandwidth ■ 4-Word Burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 800 MHz) at 400 MHz ■ Read latency of 2.

Published: Nov 6, 2016 |