CY7C1264XV18 Description
CY7C1262XV18 CY7C1264XV18 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency).
CY7C1264XV18 Key Features
- Separate independent read and write data ports
- Supports concurrent transactions
- 450 MHz clock for high bandwidth
- Two-word burst for reducing address bus frequency
- Double Data Rate (DDR) interfaces on both read and write ports
- Available in 2.5 clock cycle latency
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Echo clocks (CQ and CQ) simplify data capture in high speed
- Data valid pin (QVLD) to indicate valid data on the output