CY7C1264XV18 - 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture

This page provides the datasheet information for the CY7C1264XV18, a member of the CY7C1262XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture family.

Product Overview

Cypress Semiconductor

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Datasheet Details

Part number	CY7C1264XV18
Manufacturer	Cypress Semiconductor
File Size	1.04 MB
Description	36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
Datasheet	CY7C1264XV18 Datasheet
Additional preview pages of the CY7C1264XV18 datasheet.

CY7C1264XV18 Product details

Features

Separate independent read and write data ports.
Supports concurrent transactions.
450 MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz.
Available in 2.5 clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high speed syst.

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Other Datasheets by Cypress Semiconductor

CY7C1261V18 - 1.8V Synchronous Pipelined SRAM
CY7C1262XV18 - 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C1263KV18 - 36-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1263V18 - 1.8V Synchronous Pipelined SRAM
CY7C1263XV18 - 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
CY7C1265KV18 - 36-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1265V18 - 1.8V Synchronous Pipelined SRAM
CY7C1265XV18 - 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture

Published: Mar 14, 2017 |