Datasheet4U Logo Datasheet4U.com

CY7C1264XV18 - 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture

Download the CY7C1264XV18 datasheet PDF (CY7C1262XV18 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 36-mbit qdr ii+ xtreme sram two-word burst architecture.

Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 450 MHz clock for high bandwidth.
  • Two-word burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz.
  • Available in 2.5 clock cycle latency.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high speed syst.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1262XV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

  • CY7C1006D - 1-Mbit (256K x 4) Static RAM (Cypress)
  • CY7C1011G - 2-Mbit (128K words x 16 bit) Static RAM (Cypress)
  • CY7C1041G - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1041GE - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1041GN - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1049GN - 4-Mbit (512K words x 8 bit) Static RAM (Cypress)
  • CY7C1061DV33 - 16-Mbit (1 M X 16) Static RAM (Cypress)
  • CY7C1061G - 16-Mbit (1 M words x 16 bit) Static RAM (Cypress)
  • CY7C106D - 1-Mbit (256K x 4) Static RAM (Cypress)
  • CY7C131AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
Other Datasheets by Cypress Semiconductor
  • CY7C1261V18 - 1.8V Synchronous Pipelined SRAM
  • CY7C1262XV18 - 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
  • CY7C1263KV18 - 36-Mbit QDR II+ SRAM Four-Word Burst Architecture
  • CY7C1263V18 - 1.8V Synchronous Pipelined SRAM
  • CY7C1263XV18 - 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
  • CY7C1265KV18 - 36-Mbit QDR II+ SRAM Four-Word Burst Architecture
  • CY7C1265V18 - 1.8V Synchronous Pipelined SRAM
  • CY7C1265XV18 - 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture

Full PDF Text Transcription

Click to expand full text
CY7C1262XV18 CY7C1264XV18 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 450 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz ■ Available in 2.
Published: |