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Cypress Semiconductor Electronic Components Datasheet

CY7C1304DV25 Datasheet

9-Mbit Burst of 4 Pipelined SRAM

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PRELIMINARY
CY7C1304DV25
9-Mbit Burst of 4 Pipelined SRAM with
QDR™ Architecture
Features
• Separate independent Read and Write data ports
— Supports concurrent transactions
• 167-MHz Clock for high bandwidth
— 2.5 ns Clock-to-Valid access time
• 4-Word Burst for reducing the address bus frequency
• Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 333 MHz) @167 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew
and flight time mismatching
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL Inputs and Outputs
• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165-ball
(11x15 matrix)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG 1149.1 compatible test access port
Configurations
CY7C1304DV25 – 512K x 18
Logic Block Diagram (CY7C1304DV25)
D[17:0]
18
Functional Description
The CY7C1304DV25 is a 2.5V Synchronous Pipelined SRAM
equipped with QDR™ architecture. QDR architecture consists
of two separate ports to access the memory array. The Read
port has dedicated Data Outputs to support Read operations
and the Write port has dedicated Data Inputs to support Write
operations. QDR architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus required with common I/O devices. Access to
each port is accomplished through a common address bus.
Addresses for Read and Write addresses are latched on
alternate rising edges of the input (K) clock. Accesses to the
device’s Read and Write ports are completely independent of
one another. In order to maximize data throughput, both Read
and Write ports are equipped with Double Data Rate (DDR)
interfaces. Each address location is associated with four 18-bit
words. Since data can be transferred into and out of the device
on every rising edge of both input clock (K/K and C/C) memory
bandwidth is maximized while simplifying system design by
eliminating bus “turn-arounds.”
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
A(16:0)
17
Address
Register
Write Write Write Write
Reg Reg Reg Reg
Address
Register
17 A(16:0)
K
K CLK
Gen.
Vref
WPS
BWS[0:1]
Control
Logic
Read Data Reg.
72 36
36
Control
Logic
RPS
C
C
Reg.
Reg.
Reg.
18
18
Q[17:0]
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05628 Rev. **
Revised July 29, 2004


Cypress Semiconductor Electronic Components Datasheet

CY7C1304DV25 Datasheet

9-Mbit Burst of 4 Pipelined SRAM

No Preview Available !

PRELIMINARY
CY7C1304DV25
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
CY7C1304DV25-167
167
TBD
CY7C1304DV25-133
133
TBD
CY7C1304DV25-100
100
TBD
Unit
MHz
mA
Pin Configuration – CY7C1304DV25 (Top View)
1 2 345
A NC Gnd/144M NC/36M WPS BWS1
B NC Q9 D9 A NC
C NC
NC
D10 VSS
A
D NC
D11 Q10 VSS VSS
E NC
NC Q11 VDDQ VSS
F NC Q12 D12 VDDQ VDD
G NC D13 Q13 VDDQ VDD
H NC VREF VDDQ VDDQ VDD
J NC
NC D14 VDDQ VDD
K NC
NC Q14 VDDQ VDD
L NC Q15 D15 VDDQ VSS
M NC
NC D16 VSS VSS
N NC D17 Q16 VSS A
P NC
NC Q17 A
A
R TDO TCK A A A
6
K
K
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
C
C
7
NC
BWS0
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
A
8
RPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
9 10
NC/18M Gnd/72M
NC NC
NC Q7
NC NC
NC D6
NC NC
NC NC
VDDQ VREF
NC Q4
NC D3
NC NC
NC Q1
NC NC
NC D0
A TMS
11
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Pin Definitions
Name
D[17:0]
WPS
BWS0, BWS1
A
Q[17:0]
RPS
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Outputs-
Synchronous
Input-
Synchronous
Description
Data input signals, sampled on the rising edge of K and K clocks during valid Write
operations.
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When
asserted active, a Write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D[17:0] to be ignored.
Byte Write Select 0 and 1, active LOW. Sampled on the rising edge of the K and K
clocks during Write operations. Used to select which byte is written into the device during
the current portion of the Write operations. Bytes not written remain unaltered.
BWS0 controls D[8:0] and BWS1 controls D[17:9].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte
Write Select will cause the corresponding byte of data to be ignored and not written into
the device.
Address Inputs. Sampled on the rising edge of the K clock during active Read and Write
operations. These address inputs are multiplexed for both Read and Write operations.
Internally, the device is organized as 512Kb x 18 (4 arrays each of 128Kb x 18).
Therefore, only 17 address inputs are needed to access the entire memory array. These
inputs are ignored when the appropriate port is deselected.
Data Output signals. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations or K and K when in single clock mode. When the Read port is deselected,
Q[17:0] are automatically three-stated.
Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K).
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the output
drivers are automatically three-stated following the next rising edge of the C clock. Each
read access consists of a burst of four sequential 18-bit transfers.
Document #: 38-05628 Rev. **
Page 2 of 18


Part Number CY7C1304DV25
Description 9-Mbit Burst of 4 Pipelined SRAM
Maker Cypress Semiconductor
Total Page 18 Pages
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