CY7C1311JV18 Datasheet (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: 18-Mbit QDR II SRAM 4-Word Burst Architecture.

Datasheet Details

Part number	CY7C1311JV18
Manufacturer	Cypress (now Infineon)
File Size	705.07 KB
Description	(CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture
Download	CY7C1311JV18 Download (PDF)

The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture.

QDR II architecture consists of two separate ports: the read port and the write port to access the memory array.

The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 ® Configurations CY7C1311JV18.
2M x 8 CY7C1911JV18.
2M x 9 CY7C1313JV18.
1M x 18 CY7C1315JV18.
512K x 36 Separate Independent Read and Write Data Ports.
Supports concurrent transactions 300 MHz Clock for High Bandwidth 4-word Burst for reducing Address Bus Frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz Two Input Clocks (K and K).

Part Number	Description
CY7C1311AV18	(CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1311BV18	(CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1311CV18	(CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1311KV18	18-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C131	1K x 8 Dual-Port Static RAM
CY7C1310BV18	1.8V Synchronous Pipelined SRAM
CY7C1312BV18	1.8V Synchronous Pipelined SRAM
CY7C1312KV18	18-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1313AV18	(CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1313BV18	(CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture