CY7C1311JV18 - (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture

Cypress Semiconductor

The CY7C1311JV18 by Cypress Semiconductor is a (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture. Below is the official datasheet preview.

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CY7C1311JV18 (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture by Cypress Semiconductor - Datasheet Preview — Official preview page of the **CY7C1311JV18** (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture datasheet (Cypress Semiconductor).

Datasheet Details

Part number	CY7C1311JV18
Manufacturer	Cypress Semiconductor
File Size	705.07 KB
Description	(CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture
Datasheet	CY7C1311JV18_CypressSemiconductor.pdf
Additional preview pages of the CY7C1311JV18 datasheet.

CY7C1311JV18 Product details

Description

The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture.

Features

CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 ® Configurations CY7C1311JV18.
2M x 8 CY7C1911JV18.
2M x 9 CY7C1313JV18.
1M x 18 CY7C1315JV18.
512K x 36 Separate Independent Read and Write Data Ports.
Supports concurrent transactions 300 MHz Clock for High Bandwidth 4-word Burst for reducing Address Bus Frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz Two Input Clocks (K and K).

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Other Datasheets by Cypress Semiconductor

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Published: Dec 9, 2010 |