CY7C131 Datasheet

Cypress

CY7C131

Key Features

True dual-ported memory cells, which allow simultaneous reads of the same memory location
1K x 8 organization
0.65 micron CMOS for optimum speed and power
High speed access: 15 ns
Low operating power: ICC = 110 mA (maximum)
Fully asynchronous operation
Automatic power down
Master CY7C130/130A/CY7C131/131A easily expands data bus width to 16 or more bits using slave CY7C140/CY7C141
BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY input on CY7C140/CY7C141
INT flag for port-to-port communication

Part Number	Manufacturer	Description
CY7C1372D	Cypress	18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM
CY7C1370C	Cypress	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1371S	Cypress	18-Mbit (512K x 36) Flow-Through SRAM
CY7C1383D	Cypress	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383F	Cypress	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C136AE	Cypress	1K/2K x 8 Dual-Port Static RAM
CY7C1382S	Cypress	18-Mbit (512 K x 36/1 M x 18) Pipelined SRAM
CY7C1373C	Cypress	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture
CY7C1380S	Cypress	18-Mbit (512 K x 36/1 M x 18) Pipelined SRAM
CY7C1386S	Cypress	18-Mbit (512 K x 36) Pipelined DCD Sync SRAM