- Part: CY7C1371S
- Description: 18-Mbit (512K x 36) Flow-Through SRAM
- Manufacturer: Cypress
- Size: 625.63 KB
Key Features
- No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles
- Supports up to 133-MHz bus operations with zero wait states
- Data is transferred on every clock
- Pin-compatible and functionally equivalent to ZBT™ devices
- Internally self-timed output buffer control to eliminate the need to use OE
- Registered inputs for flow through operation
- Byte Write capability
- 3.3 V/2.5 V I/O power supply (VDDQ)
- Fast clock-to-output times ❐ 6.5 ns (for 133-MHz device)
- Clock Enable (CEN) pin to enable clock and suspend operation
Datasheets by Manufacturer
- CY7C1371DV25 — Cypress — Flow-Through SRAM
- CY7C1373DV25 — Cypress — Flow-Through SRAM
- CY7C1373B — Cypress — 512K x 36/1M x 18 Flow-Thru SRAM
- CY7C1372DV25 — Cypress — 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
- CY7C1379C — Cypress — 9-Mbit (256K x 32) Flow-through SRAM
- CY7C1372KV33 — Cypress — 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
- CY7C1372KVE33 — Cypress — 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
- CY7C1372KV25 — Cypress — 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
- CY7C1373D — Cypress — 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM
- CY7C1373KV33 — Cypress — 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
