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CY7C1373KV33 - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

This page provides the datasheet information for the CY7C1373KV33, a member of the CY7C1371KV33 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM family.

Datasheet Summary

Features

  • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles.
  • Supports up to 133-MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Pin-compatible and functionally equivalent to ZBT™ devices.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Registered inputs for flow through operation.
  • Byte write capability.
  • 3.3 V/2.5 V I/O power supply (VDDQ).
  • Fast clock-to-output ti.

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Datasheet preview – CY7C1373KV33

Datasheet Details

Part number CY7C1373KV33
Manufacturer Cypress Semiconductor
File Size 0.96 MB
Description 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
Datasheet download datasheet CY7C1373KV33 Datasheet
Additional preview pages of the CY7C1373KV33 datasheet.

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Other Datasheets by Cypress Semiconductor
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  • CY7C1370KV33 - 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
  • CY7C1370KVE33 - 18-Mbit (512K x 36/1M x 18) Pipelined SRAM

Full PDF Text Transcription

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CY7C1371KV33 CY7C1371KVE33 CY7C1373KV33 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM with NoBL™ Architecture (With ECC) 18-Mbit (512K × 36/1M × 18) Flow-through SRAM with NoBL™ Architecture (With ECC) Features ■ No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock ■ Pin-compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need to use OE ■ Registered inputs for flow through operation ■ Byte write capability ■ 3.3 V/2.5 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 6.
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