- Part: CY7C1371C
- Description: 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture
- Manufacturer: Cypress
- Size: 791.68 KB
Key Features
- No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
- Can support up to 133-MHz bus operations with zero wait states - Data is transferred on every clock
- Pin compatible and functionally equivalent to ZBT™ devices
- Internally self-timed output buffer control to eliminate the need to use OE
- Registered inputs for flow-through operation
- Byte Write capability
- 3.3V/2.5V I/O power supply
- Fast clock-to-output times - 6.5 ns (for 133-MHz device) - 7.5 ns (for 117-MHz device) - 8.5 ns (for 100-MHz device)
- Clock Enable (CEN) pin to enable clock and suspend operation
- Synchronous self-timed writes
Datasheets by Manufacturer
- CY7C1371KV33 — Cypress — 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
- CY7C1371KVE33 — Cypress — 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
- CY7C1371D — Cypress — 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM
- CY7C1371DV25 — Cypress — Flow-Through SRAM
- CY7C1373DV25 — Cypress — Flow-Through SRAM
- CY7C1373B — Cypress — 512K x 36/1M x 18 Flow-Thru SRAM
- CY7C1370DV25 — Cypress — 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
- CY7C1370KVE33 — Cypress — 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
- CY7C1370B — Cypress — 512K X 36/1M X 18 Pipelined SRAM
- CY7C1372DV25 — Cypress — 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
