CY7C1371C Datasheet | Cypress

CY7C1371C CY7C1373C 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture Features - No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles - Can support up to 133-MHz bus operations with zero wait states - Data is transferred on every clock - Pin patible and functionally equivalent to ZBT™ devices - Internally self-timed output buffer control to eliminate the need to use OE - Registered inputs for flow-through operation - Byte Write capability - 3.3V/2.5V I/O power supply - Fast clock-to-output times - 6.5 ns (for 133-MHz device) - 7.5 ns (for 117-MHz device) - 8.5 ns (for 100-MHz device) - Clock Enable (CEN) pin to enable clock and...