• Part: CY7C1370C
  • Description: 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
  • Manufacturer: Cypress
  • Size: 704.25 KB
CY7C1370C Datasheet (PDF) Download
Cypress
CY7C1370C

Key Features

  • Supports 250-MHz bus operations with zero wait states - Available speed grades are 250, 225, 200 and 167 MHz
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE
  • Fully registered (inputs and outputs) for pipelined operation
  • Single 3.3V power supply
  • 3.3V/2.5V I/O power supply
  • Clock Enable (CEN) pin to suspend operation
  • Synchronous self-timed writes
  • Available in 100 TQFP, 119 BGA, and 165 fBGA packages
  • IEEE 1149.1 JTAG Boundary Scan
  • Burst capability-linear or interleaved burst order