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CY7C1378C - 9-Mbit (256K x 32) Pipelined SRAM

Description

The CY7C1378C is a 3.3V, 256K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

Features

  • Pin-compatible and functionally equivalent to ZBT® devices.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Byte Write capability.
  • 256K x 32 common I/O architecture.
  • Single 3.3V power supply (VDD).
  • Fast clock-to-output times.
  • 2.8 ns (for 250-MHz device).
  • Clock Enable (CEN) pin to suspend operation.
  • Synchronous self-timed writes.
  • Asynchronous Output Enable (OE).
  • Availab.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY7C1378C 9-Mbit (256K x 32) Pipelined SRAM with NoBL™ Architecture Features • Pin-compatible and functionally equivalent to ZBT® devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 32 common I/O architecture • Single 3.3V power supply (VDD) • Fast clock-to-output times — 2.8 ns (for 250-MHz device) • Clock Enable (CEN) pin to suspend operation • Synchronous self-timed writes • Asynchronous Output Enable (OE) • Available in JEDEC-standard lead-free 100-Pin TQFP package • Burst Capability—linear or interleaved burst order • “ZZ” Sleep mode option Functional Description[1] The CY7C1378C is a 3.
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