CY7C1378C Description
[1] The CY7C1378C is a 3.3V, 256K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1378C is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.
CY7C1378C Key Features
- Pin-patible and functionally equivalent to ZBT® devices
- Internally self-timed output buffer control to eliminate the need to use OE
- Byte Write capability
- 256K x 32 mon I/O architecture
- Single 3.3V power supply (VDD)
- Fast clock-to-output times
- 2.8 ns (for 250-MHz device)
- Clock Enable (CEN) pin to suspend operation
- Synchronous self-timed writes
- Asynchronous Output Enable (OE)