Datasheet Summary
73B
CY7C1371B CY7C1373B
512K x 36/1M x 18 Flow-Thru SRAM with NoBL™ Architecture
Features
- Pin patible and functionally equivalent to ZBT devices
- Supports 117-MHz bus operations with zero wait states
- Data is transferred on every clock
- Internally self-timed output buffer control to eliminate the need to use asynchronous OE
- Registered inputs for flow-thru operation
- Byte Write capability
- mon I/O architecture
- Fast clock-to-output times
- 7.5 ns (for 117-MHz device)
- 8.5 ns (for 100-MHz device)
- -
- -
- -
- -
- 10.0ns (for 83-MHz device) Single 3.3V
- 5% and +10% power supply VDD Separate VDDQ for 3.3V or 2.5V I/O Clock enable (CEN) pin to suspend operation Synchronous...
