CY7C1371B Description
The CY7C1371B/CY7C1373B is 3.3V, 512K × 36 and 1M × 18 synchronous flow-thru burst SRAMs, respectively designed to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371B/ CY7C1373B is equipped with the advanced No Bus Latency™ (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.
CY7C1371B Key Features
- Pin patible and functionally equivalent to ZBT devices
- Supports 117-MHz bus operations with zero wait states
- Data is transferred on every clock
- Internally self-timed output buffer control to eliminate the need to use asynchronous OE
- Registered inputs for flow-thru operation
- Byte Write capability
- mon I/O architecture
- Fast clock-to-output times
- 7.5 ns (for 117-MHz device)
- 8.5 ns (for 100-MHz device)