Datasheet4U Logo Datasheet4U.com

CY7C1371DV25 - (CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM

Download the CY7C1371DV25 datasheet PDF. This datasheet also covers the CY7C1373DV25 variant, as both devices belong to the same (cy7c1371dv25 / cy7c1373dv25) flow-through sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The CY7C1371DV25/CY7C1373DV25 is a 2.5V, 512K x 36/1M x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

Key Features

  • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.
  • Can support up to 133-MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Pin compatible and functionally equivalent to ZBT™ devices.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Registered inputs for flow-through operation.
  • Byte Write capability.
  • 2.5V core power supply (VDD).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1373DV25_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C1371C 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture Cypress
CY7C1371S 18-Mbit (512K x 36) Flow-Through SRAM Cypress
CY7C1370C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress
CY7C1370CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress
CY7C1370D 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM Cypress

Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1371D 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM
CY7C1371B (CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM
CY7C1371KV33 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1371KVE33 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1370B (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C1371DV25 www.DataSheet4U.com CY7C1373DV25 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 2.5V core power supply (VDD) • 2.5V I/O power supply (VDDQ) • Fast clock-to-output times — 6.