CY7C131A
Key Features
- True dual-ported memory cells, which allow simultaneous reads of the same memory location
- 1K x 8 organization
- 0.65 micron CMOS for optimum speed and power
- High speed access: 15 ns
- Low operating power: ICC = 110 mA (maximum)
- Fully asynchronous operation
- Automatic power down
- Master CY7C130/130A/CY7C131/131A easily expands data bus width to 16 or more bits using slave CY7C140/CY7C141
- BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY input on CY7C140/CY7C141
- INT flag for port-to-port communication
