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CY7C1382S Datasheet 18-mbit (512 K X 36/1 M X 18) Pipelined Sram

Manufacturer: Cypress (now Infineon)

Overview: CY7C1380S CY7C1382S 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined.

This datasheet includes multiple variants, all published together in a single manufacturer document.

General Description

Functional Description The CY7C1380S/CY7C1382S SRAM integrates 524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).

The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW).

Key Features

  • Supports bus operation up to 167 MHz.
  • Available speed grade is 167 MHz.
  • Registered inputs and outputs for pipelined operation.
  • 3.3 V core power supply.
  • 2.5 V or 3.3 V I/O power supply.
  • Fast clock-to-output times.
  • 3.4 ns (for 167 MHz device).
  • Provides high-performance 3-1-1-1 access rate.
  • User selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences.
  • Separate processor and controller address strobes.
  • Synchro.

Similar Datasheet

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CY7C1382S Distributor