CY7C1382S Datasheet PDF - Cypress 18-Mbit (512 K x 36/1 M x 18) Pipelined SRAM Specs

CY7C1382S - 18-Mbit (512 K x 36/1 M x 18) Pipelined SRAM

This page provides the datasheet information for the CY7C1382S, a member of the CY7C1380S 18-Mbit (512 K x 36/1 M x 18) Pipelined SRAM family.

Datasheet Summary

Description

The CY7C1380S/CY7C1382S SRAM integrates 524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

Features

Supports bus operation up to 167 MHz.
Available speed grade is 167 MHz.
Registered inputs and outputs for pipelined operation.
3.3 V core power supply.
2.5 V or 3.3 V I/O power supply.
Fast clock-to-output times.
3.4 ns (for 167 MHz device).
Provides high-performance 3-1-1-1 access rate.
User selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences.
Separate processor and controller address strobes.
Synchro.

Datasheet Details

Part number	CY7C1382S
Manufacturer	Cypress
File Size	733.83 KB
Description	18-Mbit (512 K x 36/1 M x 18) Pipelined SRAM
Datasheet	CY7C1382S Datasheet
Additional preview pages of the CY7C1382S datasheet.

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Full PDF Text Transcription

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CY7C1380S CY7C1382S 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Features ■ Supports bus operation up to 167 MHz ■ Available speed grade is 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V or 3.3 V I/O power supply ■ Fast clock-to-output times ❐ 3.

Published: Oct 2, 2016 |