CY7C1382S Overview
All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin.
CY7C1382S Key Features
- Supports bus operation up to 167 MHz
- Available speed grade is 167 MHz
- Registered inputs and outputs for pipelined operation
- 3.3 V core power supply
- 2.5 V or 3.3 V I/O power supply
- Fast clock-to-output times
- 3.4 ns (for 167 MHz device)
- Provides high-performance 3-1-1-1 access rate
- User selectable burst counter supporting Intel Pentium®
- Separate processor and controller address strobes
