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CY7C1380CV25 - (CY7C1380CV25 / CY7C1382CV25) 512K x 36/1M x 18 Pipelined SRAM

General Description

The Cypress Synchronous Burst SRAM family employs highspeed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology.

Each memory cell consists of six transistors.

Key Features

  • Fast clock speed: 250, 225, 200, 167 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 2.6, 2.8, 3.0, 3.4 ns Optimal for depth expansion Single 2.5V ±5% power supply Common data inputs and data outputs Byte Write Enable and Global Write control Chip enable for address pipeline Address, data, and control registers Internally self-timed Write cycle Burst control pins (.

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Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1380C 18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380BV25 512K x 36 / 1 Mb x 18 Pipelined SRAM
CY7C1380D 18-Mbit Pipelined SRAM
CY7C1380DV33 18-Mbit Pipelined SRAM
CY7C1380F 18-Mbit Pipelined SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com 380CV25 PRELIMINARY CY7C1380CV25 CY7C1382CV25 512K x 36/1M x 18 Pipelined SRAM Features • • • • • • • • • • • Fast clock speed: 250, 225, 200, 167 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 2.6, 2.8, 3.0, 3.4 ns Optimal for depth expansion Single 2.5V ±5% power supply Common data inputs and data outputs Byte Write Enable and Global Write control Chip enable for address pipeline Address, data, and control registers Internally self-timed Write cycle Burst control pins (interleaved or linear burst sequence) • Automatic power-down available using ZZ mode or CE deselect • Available in 119-ball bump BGA, 165-ball FBGA and 100-pin TQFP packages • JTAG boundary scan for BGA packaging version (CLK).