CY7C1380CV25
Overview
- Fast clock speed: 250, 225, 200, 167 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 2.6, 2.8, 3.0, 3.4 ns Optimal for depth expansion Single 2.5V ±5% power supply Common data inputs and data outputs Byte Write Enable and Global Write control Chip enable for address pipeline Address, data, and control registers Internally self-timed Write cycle Burst control pins (interleaved or linear burst sequence)
- Automatic power-down available using ZZ mode or CE deselect
- Available in 119-ball bump BGA, 165-ball FBGA and 100-pin TQFP packages
- JTAG boundary scan for BGA packaging version (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE), burst control inputs (ADSC, ADSP, and ADV), write enables (BWa, BWb, BWc, BWd and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and burst mode control (MODE). The data (DQa,b,c,d) and the data parity (DQPa,b,c,d) outputs, enabled by OE, are also asynchronous. DQa,b,c,d and DPa,b,c,d apply to CY7C1380CV25 and DQa,b and DPa,b apply to CY7C1382CV25. a, b, c, d each are of 8 bits wide in the case of DQ and 1 bit wide in the case of DP. Addresses and chip enables are registered with either address status processor (ADSP) or address status controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BWa controls DQa and DPa. BWb controls DQb and DPb. BWc controls DQc and DPd. BWd controls DQd and DPd. BWa, BWb BWc, and BWd can be active only with BWE being LOW. GW
