CY7C1382CV25 Overview
The Cypress Synchronous Burst SRAM family employs highspeed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology. Each memory cell consists of six transistors. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input Selection Guide 250 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Shaded areas contain...
CY7C1382CV25 Key Features
- Automatic power-down available using ZZ mode or CE deselect
- Available in 119-ball bump BGA, 165-ball FBGA and 100-pin TQFP packages