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CY7C1382CV25 - (CY7C1380CV25 / CY7C1382CV25) 512K x 36/1M x 18 Pipelined SRAM

Download the CY7C1382CV25 datasheet PDF. This datasheet also covers the CY7C1380CV25 variant, as both devices belong to the same (cy7c1380cv25 / cy7c1382cv25) 512k x 36/1m x 18 pipelined sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The Cypress Synchronous Burst SRAM family employs highspeed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology.

Each memory cell consists of six transistors.

Key Features

  • Fast clock speed: 250, 225, 200, 167 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 2.6, 2.8, 3.0, 3.4 ns Optimal for depth expansion Single 2.5V ±5% power supply Common data inputs and data outputs Byte Write Enable and Global Write control Chip enable for address pipeline Address, data, and control registers Internally self-timed Write cycle Burst control pins (.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1380CV25_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com 380CV25 PRELIMINARY CY7C1380CV25 CY7C1382CV25 512K x 36/1M x 18 Pipelined SRAM Features • • • • • • • • • • • Fast clock speed: 250, 225, 200, 167 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 2.6, 2.8, 3.0, 3.4 ns Optimal for depth expansion Single 2.5V ±5% power supply Common data inputs and data outputs Byte Write Enable and Global Write control Chip enable for address pipeline Address, data, and control registers Internally self-timed Write cycle Burst control pins (interleaved or linear burst sequence) • Automatic power-down available using ZZ mode or CE deselect • Available in 119-ball bump BGA, 165-ball FBGA and 100-pin TQFP packages • JTAG boundary scan for BGA packaging version (CLK).