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CY7C1380KV33 - 18-Mbit Pipelined SRAM

General Description

The CY7C1380KV33/CY7C1382KV33 SRAM integrates 524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

Key Features

  • Supports bus operation up to 250 MHz.
  • Available speed grades are 250, 200, and 167 MHz.
  • Registered inputs and outputs for pipelined operation.
  • 3.3 V core power supply.
  • 2.5 V or 3.3 V I/O power supply.
  • Fast clock-to-output times.
  • 2.5 ns (for 250 MHz device).
  • Provides high performance 3-1-1-1 access rate.
  • Separate processor and controller address strobes.
  • Synchronous self-timed write.
  • Asynchronous output enable.
  • Single cycle chip deselec.

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📁 Similar Datasheet

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Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1380BV25 512K x 36 / 1 Mb x 18 Pipelined SRAM
CY7C1380C 18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380CV25 (CY7C1380CV25 / CY7C1382CV25) 512K x 36/1M x 18 Pipelined SRAM
CY7C1380D 18-Mbit Pipelined SRAM
CY7C1380DV33 18-Mbit Pipelined SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY7C1380KV33 CY7C1382KV33 18-Mbit (512K × 36/1M × 18) Pipelined SRAM 18-Mbit (512K × 36/1M × 18) Pipelined SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3 V core power supply ■ 2.5 V or 3.3 V I/O power supply ■ Fast clock-to-output times ❐ 2.5 ns (for 250 MHz device) ■ Provides high performance 3-1-1-1 access rate ■ Separate processor and controller address strobes ■ Synchronous self-timed write ■ Asynchronous output enable ■ Single cycle chip deselect ■ Available in JEDEC-standard Pb-free 100-pin TQFP and non Pb-free 165-ball FBGA package. ■ IEEE 1149.