Description
The CY7C1312KV18, and CY7C1314KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture..
Features
- Separate independent read and write data ports.
- Supports concurrent transactions.
- 333 MHz clock for high bandwidth.
- Two-word burst on all accesses.
- Double-data rate (DDR) interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz.
- Two input clocks (K and K) for precise DDR timing.
- SRAM uses rising edges only.
- Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches.
- Echo clocks (CQ and CQ) sim.
