CY7C1320KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture Datasheet

CY7C1320KV18 Key Features

2 M × 8 CY7C1916KV18
2 M × 9 CY7C1318KV18
1 M × 18 CY7C1320KV18
512 K × 36
SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
Supports both 1.5 V and 1.8 V I/O supply Available in 165-ball FBGA package (13 × 15 × 1.4 mm) Offered in both Pb-free a

Part Number	Description
CY7C1320AV18	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320CV18	(CY7C1xxxCV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320JV18	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C132	2K x 8 Dual-Port Static RAM