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CY7C1320KV18 Datasheet

18-Mbit DDR II SRAM Two-Word Burst Architecture

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CY7C1316KV18, CY7C1916KV18
CY7C1318KV18, CY7C1320KV18
18-Mbit DDR II SRAM
Two-Word Burst Architecture
18-Mbit DDR II SRAM Two-Word Burst Architecture
Features
Configurations
18-Mbit density (2 M × 8, 2 M × 9, 1 M × 18, 512 K × 36)
333-MHz clock for high bandwidth
Two-word burst for reducing address bus frequency
Double data rate (DDR) interfaces
(data transferred at 666 MHz) at 333 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Synchronous internally self-timed writes
DDR II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to DDR-I device with 1 cycle read latency
when DOFF is asserted LOW
1.8 V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4 V–VDD)
Supports both 1.5 V and 1.8 V I/O supply
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Phase locked loop (PLL) for accurate data placement
Selection Guide
CY7C1316KV18 – 2 M × 8
CY7C1916KV18 – 2 M × 9
CY7C1318KV18 – 1 M × 18
CY7C1320KV18 – 512 K × 36
Functional Description
The CY7C1316KV18, CY7C1916KV18, CY7C1318KV18, and
CY7C1320KV18 are 1.8 V synchronous pipelined SRAM
equipped with DDR II architecture. The DDR II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a 1-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K. Read data is
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. Each address location
is associated with two 8-bit words in the case of CY7C1316KV18
and two 9-bit words in the case of CY7C1916KV18 that burst
sequentially into or out of the device. The burst counter always
starts with a ‘0’ internally in the case of CY7C1316KV18 and
CY7C1916KV18. On CY7C1318KV18 and CY7C1320KV18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1318KV18 and two 36-bit words in the case of
CY7C1320KV18 sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Description
Maximum operating frequency
Maximum operating current
www.DataSheet4U.com
×8
×9
× 18
× 36
333 MHz
333
440
440
450
560
300 MHz
300
420
420
430
520
250 MHz
250
370
370
380
460
200 MHz
200
330
330
340
400
167 MHz
167
300
300
310
360
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-58905 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 28, 2011
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Cypress Semiconductor Electronic Components Datasheet

CY7C1320KV18 Datasheet

18-Mbit DDR II SRAM Two-Word Burst Architecture

No Preview Available !

Logic Block Diagram (CY7C1316KV18)
CY7C1316KV18, CY7C1916KV18
CY7C1318KV18, CY7C1320KV18
A(19:0)
20
LD
K
K
DOFF
VREF
R/W
NWS[1:0]
Address
Register
CLK
Gen.
Control
Logic
Write
Reg
Write
Reg
8
Read Data Reg.
16
8
8
Output
Logic
Control
R/W
C
C
Reg.
Reg.
Reg. 8
8
8
CQ
CQ
DQ[7:0]
Logic Block Diagram (CY7C1916KV18)
A(19:0)
20
LD
K
K
DOFF
Address
Register
CLK
Gen.
www.DataShVeReEtF4U.com
R/W
BWS[0]
Control
Logic
Write
Reg
Write
Reg
9
Read Data Reg.
18
9
9
Output
Logic
Control
R/W
C
C
Reg.
Reg.
Reg. 9
9
9
CQ
CQ
DQ[8:0]
Document Number: 001-58905 Rev. *C
Page 2 of 32
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Part Number CY7C1320KV18
Description 18-Mbit DDR II SRAM Two-Word Burst Architecture
Maker Cypress Semiconductor
Total Page 30 Pages
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