CY7C1321BV18 - 1.8V Synchronous Pipelined SRAM

This page provides the datasheet information for the CY7C1321BV18, a member of the CY7C1317BV18 1.8V Synchronous Pipelined SRAM family.

Product Overview

Cypress Semiconductor

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Datasheet Details

Part number	CY7C1321BV18
Manufacturer	Cypress Semiconductor
File Size	447.88 KB
Description	1.8V Synchronous Pipelined SRAM
Datasheet	CY7C1321BV18 Datasheet
Additional preview pages of the CY7C1321BV18 datasheet.

CY7C1321BV18 Product details

Description

18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) 300-MHz clock for high bandwidth 4-Word burst for reducing address bus frequency Double Data Rate (DDR) interfaces (data transferred at 600MHz) @ 300 MHz Two input clocks (K and K) for precise DDR

Features

Functional.

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Other Datasheets by Cypress Semiconductor

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Published: Nov 6, 2016 |