Download CY7C1370B Datasheet PDF
CY7C1370B page 2
Page 2
CY7C1370B page 3
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CY7C1370B Key Features

  • Zero Bus Latency, no dead cycles between Write and Read cycles
  • Fast clock speed: 200, 167, 150, and 133 MHz
  • Fast access time: 3.0, 3.4, 3.8, and 4.2 ns
  • Internally synchronized registered outputs eliminate the need to control OE
  • Single 3.3V -5% and +10% power supply VDD
  • Separate VDDQ for 3.3V or 2.5V I/O
  • Single WE (Read/Write) control pin
  • Positive clock-edge triggered address, data, and control signal registers for fully pipelined

CY7C1370B Description

The CY7C1370B and CY7C1372B SRAMs are designed to eliminate dead cycles when transitions from Read to Write or vice versa.