CY7C1393KV18 Features
* 18-Mbit density (2M × 8, 1M × 18)
* 333-MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
* Two input clocks (K and K) for precise DDR timing
* SRAM uses rising edges
CY7C1392KV18-CypressSemiconductor.pdf
Datasheet Details
CY7C1393KV18, CY7C1392KV18
Cypress Semiconductor
587.97 KB
18-mbit ddr ii sio sram two-word burst architecture.
This datasheet PDF includes multiple part numbers: CY7C1393KV18, CY7C1392KV18.
Please refer to the document for exact specifications by model.
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CY7C1393KV18 Distributor
